Analysis updated 2026-05-18
Study a real tapeout-proven Verilog design for a 100Mbps ethernet MAC and configuration protocol.
Build and run the included packet_receiver tool to sniff and decode the broadcast counter packets.
Reference the project as part of a family of open source ethernet-connected ASIC designs.
| essenceia/until_heat_death_do_us_part | yii2004/tinycodesign | doctorwkt/verilog_tic-tac-toe | |
|---|---|---|---|
| Stars | 29 | 20 | 9 |
| Language | Verilog | Verilog | Verilog |
| Last pushed | — | — | 2026-01-14 |
| Maintenance | — | — | Quiet |
| Setup difficulty | hard | hard | moderate |
| Complexity | 5/5 | 4/5 | 3/5 |
| Audience | developer | researcher | developer |
Figures from each repo's GitHub metadata at analysis time.
Requires ASIC tooling knowledge and physical hardware such as an ethernet PHY board to interact with a real chip.
Until_Heat_Death_Do_Us_Part is a real hardware chip design, written in Verilog, whose entire purpose is a joke with real engineering behind it: a counter built large enough to keep counting for roughly ten to the power of one hundred years, which is longer than the universe is expected to remain in a state where time as we know it still means much. The chip increments this giant counter constantly and, once every second, broadcasts its current value out over a 100 megabit per second ethernet connection. This is not just a simulation. The design has actually been manufactured twice as a physical chip, once as part of an experimental multi-project shuttle run called Tiny Tapeout, and again as part of a larger open source ethernet chip project called Expresso, built on 180 nanometer manufacturing technology from Global Foundries and sponsored by a hardware manufacturing service. The repository includes a small companion program called packet_receiver that a developer can build and run on their own computer to listen for these broadcast packets on their local network and print out the counter value. The author notes, tongue in cheek, that because the counter is read as a 64 bit number on the receiving side, the receiving program itself will only work correctly for the next roughly eleven thousand years, treating that as a problem for future engineers. Under the hood, the chip reuses an existing open source ethernet communication component from a related project by the same author, and defines its own simple packet formats for broadcasting the counter value and for configuring the chip's network address settings. This project is aimed at hardware engineers and ASIC designers interested in real, tapeout proven Verilog ethernet designs, wrapped around a piece of dry humor about the eventual heat death of the universe.
Until_Heat_Death_Do_Us_Part is a real, manufactured ASIC chip that counts for roughly 10^100 years and broadcasts the count over ethernet every second, as a serious engineering joke.
Mainly Verilog. The stack also includes Verilog, Ethernet, ASIC.
No license file is mentioned in the README, so usage terms are unclear.
Setup difficulty is rated hard, with roughly 1h+ to a first successful run.
Mainly developer.
This repo across BitVibe Labs
Verify against the repo before relying on details.