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essenceia/until_heat_death_do_us_part

Analysis updated 2026-05-18

29VerilogAudience · developerComplexity · 5/5Setup · hard

TLDR

Until_Heat_Death_Do_Us_Part is a real, manufactured ASIC chip that counts for roughly 10^100 years and broadcasts the count over ethernet every second, as a serious engineering joke.

Mindmap

mindmap
  root((Heat Death Counter))
    What it does
      383 bit counter
      Broadcasts over ethernet
      Tapeout proven ASIC
      packet_receiver tool
    Tech stack
      Verilog
      100Mbps Ethernet
      ASIC tapeout
    Use cases
      Ethernet MAC study
      Hardware tapeout reference
      Novelty engineering demo
    Audience
      Hardware engineers
      ASIC designers

Code map

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What do people build with it?

USE CASE 1

Study a real tapeout-proven Verilog design for a 100Mbps ethernet MAC and configuration protocol.

USE CASE 2

Build and run the included packet_receiver tool to sniff and decode the broadcast counter packets.

USE CASE 3

Reference the project as part of a family of open source ethernet-connected ASIC designs.

What is it built with?

VerilogEthernetASIC

How does it compare?

essenceia/until_heat_death_do_us_partyii2004/tinycodesigndoctorwkt/verilog_tic-tac-toe
Stars29209
LanguageVerilogVerilogVerilog
Last pushed2026-01-14
MaintenanceQuiet
Setup difficultyhardhardmoderate
Complexity5/54/53/5
Audiencedeveloperresearcherdeveloper

Figures from each repo's GitHub metadata at analysis time.

How do you get it running?

Difficulty · hard Time to first run · 1h+

Requires ASIC tooling knowledge and physical hardware such as an ethernet PHY board to interact with a real chip.

No license file is mentioned in the README, so usage terms are unclear.

In plain English

Until_Heat_Death_Do_Us_Part is a real hardware chip design, written in Verilog, whose entire purpose is a joke with real engineering behind it: a counter built large enough to keep counting for roughly ten to the power of one hundred years, which is longer than the universe is expected to remain in a state where time as we know it still means much. The chip increments this giant counter constantly and, once every second, broadcasts its current value out over a 100 megabit per second ethernet connection. This is not just a simulation. The design has actually been manufactured twice as a physical chip, once as part of an experimental multi-project shuttle run called Tiny Tapeout, and again as part of a larger open source ethernet chip project called Expresso, built on 180 nanometer manufacturing technology from Global Foundries and sponsored by a hardware manufacturing service. The repository includes a small companion program called packet_receiver that a developer can build and run on their own computer to listen for these broadcast packets on their local network and print out the counter value. The author notes, tongue in cheek, that because the counter is read as a 64 bit number on the receiving side, the receiving program itself will only work correctly for the next roughly eleven thousand years, treating that as a problem for future engineers. Under the hood, the chip reuses an existing open source ethernet communication component from a related project by the same author, and defines its own simple packet formats for broadcasting the counter value and for configuring the chip's network address settings. This project is aimed at hardware engineers and ASIC designers interested in real, tapeout proven Verilog ethernet designs, wrapped around a piece of dry humor about the eventual heat death of the universe.

Copy-paste prompts

Prompt 1
Explain how the packet_receiver tool captures and parses the ethernet frames from this ASIC.
Prompt 2
Walk me through the configuration packet format used to set this chip's MAC address and VLAN ID.
Prompt 3
How does this project reuse the Teapot ethernet wrapper from a related repository?
Prompt 4
Summarize the counter size math used to justify a 383-bit counter in this design.

Frequently asked questions

What is until_heat_death_do_us_part?

Until_Heat_Death_Do_Us_Part is a real, manufactured ASIC chip that counts for roughly 10^100 years and broadcasts the count over ethernet every second, as a serious engineering joke.

What language is until_heat_death_do_us_part written in?

Mainly Verilog. The stack also includes Verilog, Ethernet, ASIC.

What license does until_heat_death_do_us_part use?

No license file is mentioned in the README, so usage terms are unclear.

How hard is until_heat_death_do_us_part to set up?

Setup difficulty is rated hard, with roughly 1h+ to a first successful run.

Who is until_heat_death_do_us_part for?

Mainly developer.

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