dennisonbertram/chip-design

This project designs an actual computer chip that can run a tiny language model, and it walks the whole path from writing the chip's logic to producing a manufacturable layout file, using only open source tools. The chip, called nano_accel, is built to do INT4 inference, a compact numeric format that lets a small AI model fit entirely inside the chip's own memory instead of needing external storage. The model the chip runs is a small character level neural network trained from scratch on the tiny-shakespeare text dataset using numpy, then compressed down to about 208 kilobytes so it fits on chip. The project includes a verification step where a golden software model built in numpy is compared token by token against what the real chip hardware produces, and the repository reports a fully matching, bit exact result across all 32 tokens tested. Beyond simulation, the design was pushed through synthesis and place and route on the open Nangate 45 nanometer library, meaning it was turned into a real layout of standard cells with reported area, timing, power, and zero design rule violations. The README includes concrete results: a maximum clock speed near 195 MHz, about 143 milliwatts of power, and a final GDSII file, which is the standard format used to send a chip design to a factory for manufacturing. To try it, a user needs yosys, iverilog, python3 with numpy, and Docker for the place and route stage, then can run simple make commands to train the model, simulate the chip, synthesize it, or run the full physical design flow. The project also lets someone swap in a different, differently sized model and rerun the flow to see how area and timing change, or intentionally tighten the clock constraint to watch timing fail. A separate variant targets Tiny Tapeout, a shared multi-project chip manufacturing service, using a much smaller one multiply add unit design that streams model data from external memory over a four wire interface, trading speed for a design small enough to fit the tighter area budget of that program. This repository is aimed at people interested in digital chip design and hardware for AI, and assumes familiarity with hardware description languages like Verilog.