Analysis updated 2026-07-18 · repo last pushed 2026-05-10
Work through Track A to learn HDL fundamentals like state machines, UART, SPI, and PWM.
Put a RISC-V soft CPU on an FPGA and write firmware for it in C or Zig.
Learn how a CPU interfaces with memory and GPIO pins at the hardware level.
Practice open-source FPGA toolchains on a Sipeed TangNano 9K board.
| kassane/fpga_course | konano/mips32-cpu | agg23/openfpga-template | |
|---|---|---|---|
| Stars | — | — | 6 |
| Language | Verilog | Verilog | Verilog |
| Last pushed | 2026-05-10 | 2019-01-09 | 2023-12-11 |
| Maintenance | Maintained | Dormant | Dormant |
| Setup difficulty | moderate | hard | moderate |
| Complexity | 4/5 | 5/5 | 3/5 |
| Audience | developer | researcher | developer |
Figures from each repo's GitHub metadata at analysis time.
Requires a Sipeed TangNano 9K FPGA board and open-source FPGA toolchain setup.
This repository is a hands-on curriculum for learning FPGAs, programmable hardware chips that you configure by writing code describing digital circuits. Instead of running software on a fixed CPU, you're defining the circuit itself: blinking LEDs, reading button presses, talking to sensors over serial protocols, and eventually building a tiny computer inside the chip. The course targets the Sipeed TangNano 9K board and uses entirely open-source tooling, meaning you don't need to pay for proprietary software. It's organized into two tracks. Track A teaches hardware description language fundamentals, starting with a simple LED blink and progressing through combinational logic, state machines, UART serial communication, SPI, and PWM brightness control. Track B goes further by putting a complete soft CPU (a RISC-V processor called PicoRV32) onto the FPGA, then writing firmware for it in C and Zig, effectively running software on hardware you built yourself. This would suit someone learning digital design or embedded systems who wants practical, build-it-yourself experience rather than just theory. A hobbyist might work through Track A to understand how protocols like UART and SPI actually work at the signal level. A more advanced learner could use Track B to explore the intersection of hardware and software, how a CPU interfaces with memory and GPIO pins, and how you'd program it without a standard library. The project stands out for committing to open-source toolchains, which is still uncommon in the FPGA world where vendor-locked proprietary software is the norm. Track B's choice of Zig for firmware is also unusual, it leans into compile-time features and type-safe memory-mapped I/O rather than the more typical C approach. An Intel DE10 track is listed as work-in-progress but not yet complete.
A hands-on FPGA curriculum using open-source tools that teaches hardware description from LED blinks up to running a RISC-V soft CPU with C and Zig firmware.
Mainly Verilog. The stack also includes Verilog, PicoRV32, RISC-V.
Maintained — commit in last 6 months (last push 2026-05-10).
The README doesn't specify license details.
Setup difficulty is rated moderate, with roughly 1h+ to a first successful run.
Mainly developer.
This repo across BitVibe Labs
Verify against the repo before relying on details.