zhanghai/orgexp

The repository "orgexp" contains materials for a computer organization course at Zhejiang University, taught by Shi Qingsong. It is a collection of lab assignments designed to help students learn how the internal components of a computer processor are built from the ground up. The project is written in Verilog, a language used to describe hardware. Instead of writing software that runs on a computer, Verilog describes the actual physical circuits, things like logic gates, memory, and data pathways. Through these lab exercises, a student essentially wires together the pieces of a simplified processor, learning how a CPU fetches instructions, does math, and moves data around. The intended audience is university students taking a computer organization class, likely at Zhejiang University or a similar institution. If you are enrolled in that course, the repo gives you a set of experiment frameworks to work from. For a beginner trying to understand computer hardware on their own, the files offer a concrete example of what a typical undergraduate sees when learning processor design for the first time. The README doesn't go into detail about the contents or provide usage instructions. There is no documentation explaining the individual labs, how to run the Verilog code, or what tools are needed. Anyone using the project would likely need accompanying course materials or prior knowledge of hardware simulation tools to make sense of the files.