opencorelabsx/axi-qspi-controller

This project is a hardware design, not a software application. It is a chip component, written in SystemVerilog, that lets a processor talk to Quad SPI flash memory, a common type of storage chip used in microcontrollers, systems on a chip, and RISC-V based boards. It is meant to be included as a building block inside a larger chip design rather than run as a program. The controller connects to the rest of a chip design using AXI, a standard on-chip communication protocol. It offers a register interface for configuration and a separate memory-mapped interface that lets the processor read directly from the flash chip as if it were regular memory, a technique called execute-in-place, or XIP. This means code stored on the flash chip can potentially run directly without first being copied into faster memory. It supports three flash communication speeds: standard single-wire SPI, dual-wire SPI, and quad-wire SPI, along with common flash operations like reading, programming, erasing, checking status, and reading the chip's identification number. Data moves through the controller using small first-in-first-out buffers, and the design can raise interrupts when a transfer finishes or when an error occurs. Several status flags let the connected processor check whether the controller is busy, done, or has hit an error. The repository includes the RTL source code, a file list for compiling it, and a Makefile that runs Verilator, an open-source tool for checking the design for coding mistakes before it is used in a real chip. The project is released under the MIT license.