amoslee2026/babel

★ 20SystemVerilogAudience · researcherComplexity · 5/5Setup · hard

Mindmap

mindmap
  root((babel))
    What it does
      Automates chip design
      5 AI agent stages
      Plain language input
    Tech Stack
      SystemVerilog
      Yosys synthesis
      Verilator simulation
      Magic layout
    Use Cases
      UART controller design
      Research chip prototyping
      No proprietary licenses
    Audience
      Hardware researchers
      Chip design students

mindmap root((babel)) What it does Automates chip design 5 AI agent stages Plain language input Tech Stack SystemVerilog Yosys synthesis Verilator simulation Magic layout Use Cases UART controller design Research chip prototyping No proprietary licenses Audience Hardware researchers Chip design students

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Things people build with this

USE CASE 1

Design a custom chip by describing what you want in plain language and letting AI agents generate the hardware code through architecture, RTL, and synthesis stages.

USE CASE 2

Practice realistic chip design on the ASAP7 7nm process model without purchasing any proprietary EDA tool licenses.

USE CASE 3

Run automated verification and simulation on SystemVerilog hardware descriptions using Verilator and open-source tools.

USE CASE 4

Prototype digital circuits like UART controllers or ALUs with AI-guided feedback when quality checks fail.

Tech stack

SystemVerilogYosysVerilatorMagicOpenSTAKLayoutASAP7

Getting it running

Difficulty · hard Time to first run · 1day+

Requires installing multiple open-source EDA tools (Yosys, Verilator, Magic, OpenSTA, KLayout) and the ASAP7 process kit, the README is written primarily in Chinese.

No license information is mentioned in the explanation.

In plain English

Babel is a project that aims to automate chip design using AI agents and open-source tools. Designing a computer chip traditionally requires years of specialist training and expensive commercial software. Babel tries to reduce that barrier by breaking the design process into stages and assigning an AI agent to handle each one, with the agents handing off work to each other through a structured pipeline. The pipeline has five stages: architecture (deciding what the chip should do and how it is structured), RTL generation (writing the hardware description code in SystemVerilog, a language for specifying digital circuits), verification (running simulations to confirm the design behaves correctly), synthesis (converting the hardware description into a logical netlist), and physical design (placing and routing that netlist into a layout that can be sent to a fabrication process). Each stage uses a different AI agent triggered by a slash command in Claude Code. If a stage fails quality checks, it automatically sends the problem back to an earlier agent to fix. All the underlying tools are open-source: Yosys handles synthesis, Verilator runs simulations, Magic handles layout and design rule checks, OpenSTA checks timing, and KLayout exports the final layout file. The target fabrication process is ASAP7, a publicly available model of a 7-nanometer chip process developed by Arizona State University. It is a research-grade process, not a commercial one, but it allows realistic chip design practice without proprietary tool licenses. To start a design, a user describes what they want in plain language, such as a UART controller running at a certain speed, and the architect agent produces a requirement document, an architecture description, and a micro-architecture specification. Subsequent agents work from that specification. The repository's README is written almost entirely in Chinese, so users not reading Chinese will need translation to follow the detailed instructions. The project is in early public development with limited documentation in other languages.

Copy-paste prompts

Prompt 1

Using the Babel AI chip design pipeline, generate an architecture document and SystemVerilog RTL for a UART controller running at 115200 baud, then list what the verification agent should check.

Prompt 2

Walk me through what each of Babel's five AI agent stages, architecture, RTL generation, verification, synthesis, and physical design, produces for a simple 8-bit counter chip.

Prompt 3

Write a plain-language requirements description I can feed to Babel's architect agent to design a small RISC-V pipeline processor targeting the ASAP7 process.

Prompt 4

Explain how Babel's pipeline automatically sends a failed synthesis stage back to an earlier AI agent for correction, and what triggers that feedback loop.

Prompt 5

List all the open-source EDA tools Babel uses and what each one does in the chip design flow from SystemVerilog code to final layout file.

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