chipsalliance/rocket-chip

★ 3,768ScalaAudience · researcherComplexity · 5/5Setup · hard

Mindmap

mindmap
  root((rocket-chip))
    What it does
      Generates chip designs
      RISC-V processor
      Configurable output
    Tech Stack
      Scala and Chisel
      FIRRTL
      Verilog
      Verilator
    Use Cases
      FPGA prototyping
      Chip fabrication
      Architecture research
    Audience
      Hardware engineers
      Chip architects
      Researchers

mindmap root((rocket-chip)) What it does Generates chip designs RISC-V processor Configurable output Tech Stack Scala and Chisel FIRRTL Verilog Verilator Use Cases FPGA prototyping Chip fabrication Architecture research Audience Hardware engineers Chip architects Researchers

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Things people build with this

USE CASE 1

Generate a custom RISC-V processor design with your chosen cache size and core count for FPGA prototyping.

USE CASE 2

Run a generated chip design in software simulation using Verilator to test correctness before fabrication.

USE CASE 3

Use the configurable generator as a research platform for exploring new processor architecture ideas.

USE CASE 4

Produce Verilog output files that commercial chip synthesis tools can target for actual silicon production.

Tech stack

ScalaChiselFIRRTLVerilogVerilator

Getting it running

Difficulty · hard Time to first run · 1day+

Requires Scala/SBT, the RISC-V toolchain, Verilator, and multiple Git submodules, hardware design background is essential to use the output meaningfully.

Not specified in the explanation.

In plain English

Rocket Chip is a code generator that produces hardware designs for computer chips. Specifically, it outputs a type of design description called RTL (Register Transfer Level), which chip manufacturers and FPGA developers use to build processors. The project implements the RISC-V instruction set architecture, an open standard that defines how a processor interprets and runs software instructions. The generator is written in Scala and uses a hardware description language called Chisel, which is embedded in Scala. Rather than producing one fixed chip design, the project lets engineers configure and parameterize the output before generating Verilog files that synthesis and fabrication tools can consume. You can adjust things like cache size, bus width, peripheral devices, and the number of cores. The repository is organized as a collection of linked sub-repositories (called Git submodules), each handling a different piece of the system. Chisel handles the hardware description layer. Firrtl is an intermediate format that Chisel compiles to before producing Verilog. Other submodules provide floating-point arithmetic units, a RISC-V software toolchain, and a random instruction generator used for stress testing the generated processor designs. A generated chip design can be tested in software simulation using Verilator, mapped to an FPGA for prototype hardware testing, or sent through commercial chip fabrication tools for actual production. The project includes makefiles and configuration files that support all three paths. This is a research and engineering project originally from UC Berkeley, now hosted under the CHIPS Alliance open-source organization. Its audience is chip architects, hardware engineers, and academic researchers building RISC-V based processors. It is not a software library or a runnable application. It is a tool for generating the structural description of a processor, which other tools then compile into silicon or programmable logic.

Copy-paste prompts

Prompt 1

I want to generate a single-core RISC-V processor with a 32KB L1 cache using Rocket Chip. What Scala configuration class do I need to write and what make command do I run to produce the Verilog?

Prompt 2

How do I simulate a Rocket Chip-generated processor design with Verilator and run a simple RISC-V ELF binary on it?

Prompt 3

Walk me through targeting a Rocket Chip design to a Xilinx FPGA, what output files do I need and which tools consume them?

Prompt 4

I want to add a custom peripheral to a Rocket Chip design. Where in the Scala source do I attach a new TileLink device and how do I expose it to software?

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