chipsalliance/chisel

★ 4,656ScalaAudience · researcherComplexity · 5/5LicenseSetup · hard

Mindmap

mindmap
  root((chisel))
    What it does
      Design hardware chips
      Generate Verilog output
      Parameterized generators
    Tech stack
      Scala
      FIRRTL
      LLVM CIRCT
    Use cases
      ASIC chip design
      FPGA programming
      Signal processing
    Audience
      Hardware engineers
      Chip designers
      Researchers
    Getting started
      Chisel Bootcamp
      Textbook
      Standard library

mindmap root((chisel)) What it does Design hardware chips Generate Verilog output Parameterized generators Tech stack Scala FIRRTL LLVM CIRCT Use cases ASIC chip design FPGA programming Signal processing Audience Hardware engineers Chip designers Researchers Getting started Chisel Bootcamp Textbook Standard library

Click or tap to explore — scroll the page freely

Things people build with this

USE CASE 1

Design a custom FPGA circuit using Scala code and generate the Verilog needed to program it.

USE CASE 2

Build a parameterized FIR filter generator that produces different hardware configurations from a single code definition.

USE CASE 3

Create reusable hardware components like queue buffers and drop them into ASIC chip designs.

Tech stack

ScalaFIRRTLLLVM CIRCTVerilog

Getting it running

Difficulty · hard Time to first run · 1day+

Requires Scala/SBT toolchain plus LLVM CIRCT for Verilog generation, significant hardware engineering background needed.

Apache 2.0, use freely for any purpose including commercial, just keep the copyright notice and license file.

In plain English

Chisel, which stands for Constructing Hardware in a Scala Embedded Language, is a tool for designing digital hardware circuits. While most software projects produce programs that run on a computer chip, Chisel is used to design the chip itself, or at least the logic that goes inside a chip. It outputs a format called Verilog, which is the standard language chip fabricators and engineers use to describe circuits before manufacturing or simulation. What makes Chisel different from writing Verilog directly is that it is built on top of a general-purpose programming language called Scala. This means you can use programming concepts like variables, loops, and functions to describe hardware, which is much more expressive than traditional hardware description languages. Instead of writing out the same circuit pattern by hand many times, you can write a generator that produces the circuit automatically, with parameters you set. The README gives an example of an FIR filter, a common signal-processing building block: with Chisel you define the filter once and pass it a list of numbers that controls its behavior, and the tool generates the corresponding hardware for you. Chisel targets two main types of hardware: ASICs (custom chips manufactured in silicon) and FPGAs (reprogrammable chips that can be configured to act like almost any circuit). The same Chisel code can produce hardware for either target. The project includes a standard library of reusable components, such as queue buffers and arbiters, that hardware designers can drop into their projects rather than building those parts from scratch. Under the hood, Chisel converts your design into an intermediate format called FIRRTL, and then a compiler called LLVM CIRCT turns that into the final Verilog. The project is maintained under the CHIPS Alliance, an open-source organization focused on chip design tooling, and is released under the Apache 2.0 license. An interactive tutorial called the Chisel Bootcamp and an accompanying textbook are available for people getting started.

Copy-paste prompts

Prompt 1

I am using Chisel to design an FPGA. Show me how to write a parameterized adder module in Chisel that outputs Verilog.

Prompt 2

Using the Chisel standard library, how do I add a queue buffer between two hardware modules in my design?

Prompt 3

Walk me through creating a Chisel generator for a simple FIR filter with configurable coefficients.

Prompt 4

How do I compile my Chisel design through FIRRTL to get final Verilog output ready for chip fabrication?

Open on GitHub → Explain another repo

← chipsalliance on gitmyhub — every repo by this author, as a profile.

Verify against the repo before relying on details.