riscv/riscv-isa-manual

★ 4,614TeXAudience · developerComplexity · 1/5LicenseSetup · moderate

Mindmap

mindmap
  root((RISC-V ISA Manual))
    Volumes
      Unprivileged arch
      Privileged arch
      Profiles
    Audience
      Chip designers
      Compiler authors
      OS developers
    Build Methods
      Docker image
      Local build
      GitHub Actions
    License
      CC BY 4.0
      Free to share

mindmap root((RISC-V ISA Manual)) Volumes Unprivileged arch Privileged arch Profiles Audience Chip designers Compiler authors OS developers Build Methods Docker image Local build GitHub Actions License CC BY 4.0 Free to share

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Things people build with this

USE CASE 1

Look up the precise behavior of a RISC-V instruction when writing or debugging a compiler backend.

USE CASE 2

Understand the privileged architecture rules when porting an operating system or hypervisor to RISC-V.

USE CASE 3

Build the specification PDFs locally using Docker to get the latest draft before an official release.

USE CASE 4

Check the profile definitions to verify which instruction extensions a chip must support to claim compliance.

Tech stack

TeXLaTeXDockerGitHub Actions

Getting it running

Difficulty · moderate Time to first run · 30min

Building PDFs locally requires Docker, pre-built PDFs are available on the GitHub releases page.

Free to share and adapt for any purpose with attribution to the original source under Creative Commons Attribution 4.0.

In plain English

This repository holds the source files for the official RISC-V Instruction Set Manual. RISC-V is an open standard for how processors understand and execute instructions, and this manual is the formal document that defines those rules. Chip designers, compiler authors, and operating system developers use it as the authoritative reference for what a RISC-V processor is required to do. The manual is split into three volumes. Volume I covers the unprivileged architecture, which describes the instructions any RISC-V program can use. Volume II covers the privileged architecture, which describes the rules for operating systems and hypervisors that manage hardware resources. Volume III covers profiles, which are named combinations of features that define standard configurations a chip can advertise support for. The files in this repository are the original source documents written in a markup format, not polished PDFs. The official finished specifications are published on the RISC-V International website. Pre-built PDFs of the latest drafts are available on the GitHub releases page, and HTML snapshots of the most recent commit can be viewed directly in a browser. If you want to build the documents yourself, the recommended method uses a Docker image maintained by the RISC-V project, which handles all the required formatting tools automatically. The repository also supports local builds and automated GitHub Actions builds for those who prefer different workflows. The content is licensed under Creative Commons Attribution 4.0, which means anyone can share and adapt it as long as they credit the original source.

Copy-paste prompts

Prompt 1

I'm implementing a RISC-V emulator. What does the ISA manual say about how integer overflow is handled in ADD and ADDI instructions?

Prompt 2

I'm writing a RISC-V OS kernel. Explain what the privileged architecture volume says about supervisor mode and the satp register for virtual memory.

Prompt 3

How do I build the RISC-V ISA manual PDFs locally using the Docker image? What command do I run from the repo root?

Prompt 4

What RISC-V profiles are defined in Volume III and what do they mean for hardware compatibility and software portability?

Open on GitHub → Explain another repo

← riscv on gitmyhub — every repo by this author, as a profile.

Verify against the repo before relying on details.