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qedady/risc-v-simulator

Analysis updated 2026-07-17 · repo last pushed 2022-09-28

★ 1C++Audience · researcherComplexity · 3/5DormantSetup · moderate

TLDR

An educational RISC-V assembly simulator that steps through code one instruction at a time, showing register and memory changes as they happen.

Mindmap

mindmap
  root((repo))
    What it does
      Simulates RISC-V
      Steps instruction by instruction
      Shows register state
    Tech stack
      C++
      RISC-V assembly
    Use cases
      Learn computer organization
      Debug assembly code
      Verify C to assembly translation
    Audience
      Students
      Researchers

Code map

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What do people build with it?

USE CASE 1

Step through RISC-V assembly instructions to see register and memory changes.

USE CASE 2

Debug hand-written or compiler-generated assembly code.

USE CASE 3

Verify that C code translated to assembly behaves correctly.

USE CASE 4

Learn computer organization concepts by watching execution in slow motion.

What is it built with?

C++RISC-V

How does it compare?

qedady/risc-v-simulatorallentdan/shape_based_matchingbenagastov/bindweb-nim-wasm-compiler
Stars111
LanguageC++C++C++
Last pushed2022-09-282019-03-01—
MaintenanceDormantDormant—
Setup difficultymoderatemoderateeasy
Complexity3/53/55/5
Audienceresearcherdeveloperdeveloper

Figures from each repo's GitHub metadata at analysis time.

How do you get it running?

Difficulty · moderate Time to first run · 1h+

Course project from Spring 2022, built for learning, not production use.

Copy-paste prompts

Prompt 1
Explain how this RISC-V simulator shows register and memory changes after each instruction.
Prompt 2
Show me how to write a test assembly file and initial memory values for this simulator.
Prompt 3
Help me use this tool to debug a piece of RISC-V assembly I wrote.
Prompt 4
What special instructions does this simulator use to stop execution, and why?
Prompt 5
Walk me through the project report to understand the simulator's design decisions.

Frequently asked questions

What is risc-v-simulator?

An educational RISC-V assembly simulator that steps through code one instruction at a time, showing register and memory changes as they happen.

What language is risc-v-simulator written in?

Mainly C++. The stack also includes C++, RISC-V.

Is risc-v-simulator actively maintained?

Dormant — no commits in 2+ years (last push 2022-09-28).

How hard is risc-v-simulator to set up?

Setup difficulty is rated moderate, with roughly 1h+ to a first successful run.

Who is risc-v-simulator for?

Mainly researcher.

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