explaingit

mfolejewski/pcie_mux

Analysis updated 2026-05-18

14NoneAudience · developerComplexity · 5/5LicenseSetup · hard

TLDR

An open hardware design for a PCIe Gen2/Gen3 analog switch that routes one PCIe lane between two endpoints.

Mindmap

mindmap
  root((PCIe MUX))
    What it does
      Switches one PCIe lane
      Routes between two endpoints
      Signal integrity at Gen3
    Tech stack
      Altium Designer
      KiCad import
    Use cases
      Reuse in a carrier board
      Study PCB routing
      Import into KiCad
    Audience
      Hardware engineers
      Embedded designers

Code map

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filefunction / class

What do people build with it?

USE CASE 1

Reuse this schematic to switch a single PCIe lane between two endpoints in your own carrier board.

USE CASE 2

Study a real example of high speed differential pair PCB routing for PCIe signals.

USE CASE 3

Import the Altium design into KiCad to inspect or adapt the layout.

What is it built with?

Altium DesignerKiCad

How does it compare?

mfolejewski/pcie_muxsuqiyue2001/vibe-coding-prdstealthyboy93/bibata-catppuccin-cursor
Stars141619
LanguageNoneNoneNone
Setup difficultyhardeasyeasy
Complexity5/51/51/5
Audiencedevelopervibe codergeneral

Figures from each repo's GitHub metadata at analysis time.

How do you get it running?

Difficulty · hard Time to first run · 1day+

This is a hardware PCB design, not software, and requires fabrication and assembly to use.

You can use and modify the design, including commercially, but any modified version you distribute must stay under the same open hardware license.

In plain English

This repository documents a hardware circuit design: a one to two analog multiplexer that lets a single PCIe lane be switched between two different endpoints while keeping the signal clean enough to run at PCIe Generation 2 or Generation 3 speeds. It is meant for engineers building embedded systems or carrier boards, not for anyone looking for software to install. The high speed differential signals, meaning the transmit, receive, and reference clock lines, are switched using a Texas Instruments chip built for exactly this purpose and rated for data rates well above what PCIe Gen3 needs. Supporting control signals like reset, wake, and clock request are handled separately by smaller analog switch chips. The design was built for a real product called MirkoPC, where it automatically decides which device gets the PCIe connection: if a solid state drive is plugged into the M.2 slot, the system routes PCIe to it, and if that slot is empty, it falls back to an external connector instead, with two LEDs showing which path is currently active. The included PCB layout follows careful high speed design practices, including controlled spacing between paired signal traces, tight matching between the two wires in each pair, and extra grounding vias placed wherever the signal moves between layers. The design files are provided in Altium Designer's format, though the repository notes that KiCad users can import Altium projects directly through KiCad's own importer. Documentation includes schematics as PDF and image files, high resolution photos of the finished board, and pictures from the real MirkoPC product it was built for. The repository is explicit that this is provided for educational and reference use, with no warranty, and that anyone using the design is responsible for verifying it themselves before manufacturing. It is licensed under the CERN Open Hardware Licence, Strongly Reciprocal variant, which requires that any distributed modifications stay open under the same license.

Copy-paste prompts

Prompt 1
Explain how the HD3SS3412 chip in this PCIe MUX design switches high speed differential signals.
Prompt 2
Walk me through importing this Altium PCIe_MUX project into KiCad using its native importer.
Prompt 3
Summarize the PCB routing rules this design follows for differential pair spacing and via stitching.
Prompt 4
What does the CERN-OHL-S-2.0 license require if I modify and distribute this PCIe mux design?

Frequently asked questions

What is pcie_mux?

An open hardware design for a PCIe Gen2/Gen3 analog switch that routes one PCIe lane between two endpoints.

What language is pcie_mux written in?

Mainly None. The stack also includes Altium Designer, KiCad.

What license does pcie_mux use?

You can use and modify the design, including commercially, but any modified version you distribute must stay under the same open hardware license.

How hard is pcie_mux to set up?

Setup difficulty is rated hard, with roughly 1day+ to a first successful run.

Who is pcie_mux for?

Mainly developer.

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