khenderson20/clearcore

clearCore is a simulator for a MIPS processor, the type of chip taught in introductory computer architecture courses. Rather than just running programs, it visualizes exactly what happens inside the processor cycle by cycle: you can see each instruction move through the five pipeline stages, watch the system stall when one instruction needs the result of the one before it, and see the forwarding paths that resolve those conflicts highlighted in real time. The tool was built for learning. Computer architecture courses use the MIPS design as a teaching example because it cleanly illustrates how real processors work: how instructions are decoded, how calculations happen, how results are written back, and why hazards slow things down. clearCore makes those abstract concepts visible by showing the pipeline state graphically rather than just producing output. There are three interfaces included. A desktop GUI built with the Qt toolkit shows dockable panels with a code editor, a register view, a hex memory dump, a pipeline trace grid, and statistics. A second GUI written in a more modern Qt style covers the same ground. A terminal UI runs entirely in the keyboard and works over SSH, which is useful for remote access or headless environments. All three share the same simulation core, so the behavior is identical across all of them. You can type MIPS assembly directly into the built-in editor and step through execution, or load a compiled MIPS binary file and debug it with a real debugger called GDB connected through a remote stub. The simulator supports two execution modes: a simplified single-cycle version that processes one instruction at a time, and the five-stage pipeline that matches what real processors use. Building it requires a C++20 compiler, CMake, and optionally Qt6 for the desktop GUIs. The terminal-only build has no Qt dependency. The license is MIT, so it can be used freely for any purpose including commercial or academic work.