ikarthikmb/duck-server

Duck Server is a hardware project, not a typical piece of software you install and run. It designs a computer chip that can take over heavy computing tasks from a phone, laptop, or other client device and send the results back wirelessly to a screen. Think of it as offloading the hard work to a separate box so your everyday devices do not have to strain to do it themselves. The chip design includes several different processing units working together. There is a general purpose processor built around the RISC V instruction set, a component that quickly routes incoming work to the right processor, a specialized chip section for running neural network style calculations, and a vector processing unit for handling many numbers at once, similar in spirit to a graphics card. All of these pieces are described in a hardware description language called SystemVerilog, which is used to design chips before they are physically manufactured. According to the project's status table, the general purpose processor and the task routing component are complete, the neural network processing unit is complete and capable of a measured amount of computational throughput, and the vector processing component has an early version working. A wireless connection piece needed to send results to a screen is planned but not yet built. Testing this kind of project requires simulating the chip design rather than running normal code. The README describes using Docker to run a simulation environment with specific verification tools, and lists nine named tests that check different parts of the processor and neural network unit. Some tests pass completely while at least one has a documented open issue. The repository also lists several well known open source chip projects that inspired parts of its design, including work from academic labs and an existing open source RISC V processor project. This is a research and hobbyist hardware project rather than a ready to use product, aimed at people already familiar with chip design and hardware verification workflows.