haouo/chisel-hdl-guide

★ 14Audience · researcherComplexity · 4/5LicenseSetup · hard

Mindmap

mindmap
  root((chisel-hdl-guide))
    Content
      14 chapters
      Basic circuits
      Processor pipelines
    Topics
      Chisel types
      State machines
      Diplomacy TileLink
      Formal verification
    Examples
      Wildcat processor
      Register file
      Queue circuits
    Setup
      Java JDK
      sbt build tool
      Verilator sim

mindmap root((chisel-hdl-guide)) Content 14 chapters Basic circuits Processor pipelines Topics Chisel types State machines Diplomacy TileLink Formal verification Examples Wildcat processor Register file Queue circuits Setup Java JDK sbt build tool Verilator sim

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Things people build with this

USE CASE 1

Learn Chisel hardware description language from scratch if you know digital logic but not Scala

USE CASE 2

Build and simulate example circuits (counters, register files, queues, simple processors) using the included test suite

USE CASE 3

Generate SystemVerilog output from Chisel designs for use in FPGA or ASIC toolchains

USE CASE 4

Study a complete RISC-V pipeline implementation in the Wildcat processor as a hands-on reference

Tech stack

ChiselScalaJavasbtVerilator

Getting it running

Difficulty · hard Time to first run · 1h+

Requires Java JDK and sbt for building, Verilator is needed to run simulations.

Code examples are MIT licensed, use freely for any purpose including commercial, as long as you keep the copyright notice.

In plain English

This repository is a Traditional Chinese tutorial guide for Chisel, a hardware description language used to design digital circuits. Unlike software programming languages that run on a computer, Chisel is used to describe the logic of chips and other hardware. The guide is written for readers who already understand basic digital logic but have not used Scala, the programming language that Chisel is built on. The content spans 14 chapters and roughly 4,300 lines of text, covering everything from basic circuit constructs to building a full chip-on-a-chip generator in the style used by the Chipyard research project at Berkeley. The chapters progress through types and registers, arithmetic logic units, state machines, handshake-based communication interfaces, generator patterns, simple processor pipelines, memory and clock domain handling, formal verification basics, and advanced interconnect frameworks called Diplomacy and TileLink. The repository also contains a set of example projects that implement the circuit modules described in the guide. These examples compile and run through simulation using a tool called Verilator, and all nine included tests pass. The examples cover a range of circuits including counters, a register file, a queue, and a simple processor called Wildcat. A single command can generate SystemVerilog output for ten top-level modules. The guide uses ChiselSim as its testing framework, which is the current official approach, and explicitly notes that the older ChiselTest framework has been deprecated. The guide targets Chisel version 7.13.0 with Scala 2.13.18. Running the examples requires a Java development kit and the sbt build tool, simulation additionally requires Verilator. The written content is credited as an original derivative of Martin Schoeberl's book "Digital Design with Chisel" and the official Chisel documentation. Code is released under the MIT license.

Copy-paste prompts

Prompt 1

I want to follow chisel-hdl-guide to build my first register file in Chisel. What do I need to install and how do I run the first example?

Prompt 2

Using chisel-hdl-guide, how do I generate SystemVerilog output for the Wildcat processor design and simulate it with Verilator?

Prompt 3

Walk me through the handshake interface chapter of chisel-hdl-guide, what is the Decoupled pattern in Chisel and when should I use it?

Prompt 4

How do I set up sbt for the chisel-hdl-guide examples on a new machine and run all nine included tests?

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