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chateda-ichip/awesome-ai-for-chip-design

Analysis updated 2026-05-18

21Audience · researcherComplexity · 1/5LicenseSetup · easy

TLDR

A curated reading list of academic papers and tools on using AI and large language models across every stage of designing computer chips.

Mindmap

mindmap
  root((AI for Chip Design))
    What it does
      Curated list of 329 papers
      Spans 2023 to 2026
      18 categories
    Design stages covered
      Specification and HLS
      RTL generation
      Verification and debug
      Physical design and PPA
    Domains
      Analog and mixed signal
      FPGA
      Hardware security
    Foundations
      Foundation models
      Benchmarks and datasets
      Multi agent systems
    Audience
      Hardware researchers
      EDA tool builders

Code map

Detail Auto

An interactive map of this repo's files and how they connect — its source is parsed live in your browser. Click Visualize to build it.

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What do people build with it?

USE CASE 1

Find recent research papers on using LLMs to generate or verify chip hardware code.

USE CASE 2

Survey what AI techniques exist for a specific chip-design stage, such as physical design or verification.

USE CASE 3

Discover benchmark datasets used to evaluate AI models on hardware design tasks.

USE CASE 4

Track multi-agent AI systems and EDA copilot tools built for chip design workflows.

How does it compare?

chateda-ichip/awesome-ai-for-chip-design0whitedev/detranspiler0xluk3/zk-resources
Stars212121
LanguagePython
Setup difficultyeasyhardeasy
Complexity1/54/51/5
Audienceresearcherdeveloperresearcher

Figures from each repo's GitHub metadata at analysis time.

How do you get it running?

Difficulty · easy Time to first run · 5min
Placed in the public domain, anyone can copy, modify, or reuse it for any purpose without restriction.

In plain English

This repository is not software you run. It is a reading list: a large, organized collection of links to academic papers and tools about using artificial intelligence, especially large language models, to help design computer chips. As of this listing it tracks 329 papers sorted into 18 categories, with 403 total entries spanning 2023 through 2026. Designing a computer chip goes through many stages, from writing down what the chip should do, to generating the low-level hardware description code, to checking that design for bugs, to laying out the physical circuit, to testing the finished part. This list organizes papers according to where in that process the AI technique applies. Front-end topics include turning a specification into a design, generating RTL code (the hardware equivalent of source code), verification and testbench generation, and bug fixing. Back-end topics include logic synthesis and physical design, where the goal is often optimizing for power, performance, and area. There are also sections for specialized domains like analog and mixed-signal circuits, FPGAs, hardware security, and AI accelerator chips themselves. Beyond the design-flow categories, the list also tracks the underlying building blocks: foundation models trained specifically for hardware tasks, benchmark datasets used to evaluate them, techniques like retrieval-augmented generation, reinforcement learning, prompting, and fine-tuning as applied to chip design, multi-agent systems where several AI agents collaborate on a design task, and copilot tools built for existing electronic design automation (EDA) software. A final section links to broader survey papers. The project makes clear that being included in the list does not mean the maintainers endorse or vouch for a paper, and that the categorization is a best effort the community can correct through issues or pull requests. It is released under the CC0 1.0 public domain license, meaning anyone can reuse the list freely. The full README is longer than what was shown.

Copy-paste prompts

Prompt 1
Using this awesome list, summarize the main AI approaches to RTL generation for hardware design.
Prompt 2
Pull out the papers in this list related to verification and testbench generation and summarize each in one sentence.
Prompt 3
Explain what High-Level Synthesis (HLS) is and how the papers in this list apply LLMs to it.
Prompt 4
List the multi-agent frameworks for chip design mentioned in this repo and what problem each one targets.

Frequently asked questions

What is awesome-ai-for-chip-design?

A curated reading list of academic papers and tools on using AI and large language models across every stage of designing computer chips.

What license does awesome-ai-for-chip-design use?

Placed in the public domain, anyone can copy, modify, or reuse it for any purpose without restriction.

How hard is awesome-ai-for-chip-design to set up?

Setup difficulty is rated easy, with roughly 5min to a first successful run.

Who is awesome-ai-for-chip-design for?

Mainly researcher.

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