Analysis updated 2026-05-18
Find recent research papers on using LLMs to generate or verify chip hardware code.
Survey what AI techniques exist for a specific chip-design stage, such as physical design or verification.
Discover benchmark datasets used to evaluate AI models on hardware design tasks.
Track multi-agent AI systems and EDA copilot tools built for chip design workflows.
| chateda-ichip/awesome-ai-for-chip-design | 0whitedev/detranspiler | 0xluk3/zk-resources | |
|---|---|---|---|
| Stars | 21 | 21 | 21 |
| Language | — | Python | — |
| Setup difficulty | easy | hard | easy |
| Complexity | 1/5 | 4/5 | 1/5 |
| Audience | researcher | developer | researcher |
Figures from each repo's GitHub metadata at analysis time.
This repository is not software you run. It is a reading list: a large, organized collection of links to academic papers and tools about using artificial intelligence, especially large language models, to help design computer chips. As of this listing it tracks 329 papers sorted into 18 categories, with 403 total entries spanning 2023 through 2026. Designing a computer chip goes through many stages, from writing down what the chip should do, to generating the low-level hardware description code, to checking that design for bugs, to laying out the physical circuit, to testing the finished part. This list organizes papers according to where in that process the AI technique applies. Front-end topics include turning a specification into a design, generating RTL code (the hardware equivalent of source code), verification and testbench generation, and bug fixing. Back-end topics include logic synthesis and physical design, where the goal is often optimizing for power, performance, and area. There are also sections for specialized domains like analog and mixed-signal circuits, FPGAs, hardware security, and AI accelerator chips themselves. Beyond the design-flow categories, the list also tracks the underlying building blocks: foundation models trained specifically for hardware tasks, benchmark datasets used to evaluate them, techniques like retrieval-augmented generation, reinforcement learning, prompting, and fine-tuning as applied to chip design, multi-agent systems where several AI agents collaborate on a design task, and copilot tools built for existing electronic design automation (EDA) software. A final section links to broader survey papers. The project makes clear that being included in the list does not mean the maintainers endorse or vouch for a paper, and that the categorization is a best effort the community can correct through issues or pull requests. It is released under the CC0 1.0 public domain license, meaning anyone can reuse the list freely. The full README is longer than what was shown.
A curated reading list of academic papers and tools on using AI and large language models across every stage of designing computer chips.
Placed in the public domain, anyone can copy, modify, or reuse it for any purpose without restriction.
Setup difficulty is rated easy, with roughly 5min to a first successful run.
Mainly researcher.
This repo across BitVibe Labs
Verify against the repo before relying on details.