baowenbo/riscv

This repository, riscv, contains a 32-bit processor design based on the open RISC-V instruction set. It lets hardware engineers embed a working CPU into custom chips or reconfigurable FPGA boards without paying licensing fees to proprietary architecture vendors like ARM. The project also includes a software simulator, so you can test RISC-V programs on your computer even without physical silicon. At its core, the processor is written in Verilog, a language used to describe physical hardware circuits. It handles standard integer math, multiply/divide operations, and supports different privilege levels so it can run an operating system like Linux. The design is pipelined, meaning it overlaps multiple instruction steps for speed, and includes optional caches and memory management. Engineers verified correctness using Google's random instruction testing tools and reference simulation models. The repository provides two example setups: one with built-in memory for simple projects, and another with separate instruction and data caches for better performance. Chip designers, FPGA hobbyists, and embedded systems engineers would use this when building a device that needs a custom processor. For instance, someone creating a specialized IoT device or a custom microcontroller can drop this core into their design, add their peripherals, and run standard RISC-V software on it. The configurable options let them trade off features against silicon area, enabling multiply and divide support only when needed, or adjusting cache boundaries to match their memory layout. Performance-wise, the core achieves moderate benchmarks of about 2.94 CoreMarks per MHz and 1.25 DMIPS per MHz. The author notes that a higher-performance variant with dual-issue and branch prediction is available separately for projects needing more speed. This particular version targets a balance of simplicity and capability, including enough memory management support to boot Linux in software-emulated mode.